A 0.6mW/Gbps, 6.4-8.0Gbps serial link receiver using local injection-locked ring oscillators in 90nm CMOS

This paper describes a quad-channel, 6.4-8Gbps serial link receiver testchip using a global forwarded clock distribution coupled to local injection-locked ring oscillators in 90nm CMOS. Each receiver consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, a...

Full description

Saved in:
Bibliographic Details
Main Authors: Hu, Kangmin, Jiang, Tao, Wang, Jingguang, O'Mahony, Frank, Chiang, Patrick Yin
Format: Conference Proceeding
Language:English
Subjects:
Area measurement
Backplanes
Bit error rate
Clocks
CMOS process
Demultiplexing
Equalizers
injection-locked oscillator
Power measurement
receiver
Ring oscillators
Serial link
Testing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper describes a quad-channel, 6.4-8Gbps serial link receiver testchip using a global forwarded clock distribution coupled to local injection-locked ring oscillators in 90nm CMOS. Each receiver consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator for greater than one UI of phase deskew. Measured results show a 6.4-7.2Gbps data rate with BER ≪ 10 −15 across 10cm of FR4 backplane, and 8.0Gpbs data rate with direct input. Designed in a 1.2V, 90nm CMOS process, the area of each receiver is 0.0174mm 2 , with a measured power efficiency of 0.6mW/Gbps.
ISSN:2158-5601
2158-5636