A 12-Gb/s transceiver in 32-nm bulk CMOS

A 12-Gb/s transceiver in 32-nm bulk CMOS in described. Features include an 8.8-12.4-GHz LC-PLL with 0.4-ps jitter; a full-swing DLL and phase interpolator with LSB=2.6 ps and DNL≪1.2 ps; a 4.2-mW receiver front end with de-muxing comparator and precharge removal latch; and an all-digital duty cycle...

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Bibliographic Details
Main Authors: Joshi, Sopan, Liao, Jason T.-S., Fan, Yongping, Hyvonen, Sami, Nagarajan, Mahalingam, Rizk, Jad, Lee, Hyung-Jin, Young, Ian
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Clocks
Digital filters
PD control
Phase frequency detector
Transceivers
Very large scale integration
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Summary:A 12-Gb/s transceiver in 32-nm bulk CMOS in described. Features include an 8.8-12.4-GHz LC-PLL with 0.4-ps jitter; a full-swing DLL and phase interpolator with LSB=2.6 ps and DNL≪1.2 ps; a 4.2-mW receiver front end with de-muxing comparator and precharge removal latch; and an all-digital duty cycle correction (DCC) loop. The transceiver receives and transmits PRBS23 data at 12 Gb/s with BER≪10 −12 over a 6-in FR4 channel with 10 dB of loss, while consuming 37.8 mW (3.15 pJ/bit) from a 1-V supply, not including clock generation. A chip-to-chip link transmits and receives PRBS15 data at 11.6 Gb/s with BER≪10 −12 over a 12-in. FR4 channel.
ISSN:2158-5601
2158-5636