Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding

In this paper, we introduce a high-level simulation methodology for the modeling of multicore video processing architectures. This method allows design space explorations of parallel video processing applications (VPAs). It is used to test the performance of running a VPA on arbitrary virtual hardwa...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 2009-11, Vol.19 (11), p.1667-1679
Main Authors: Seitner, F.H., Bleyer, M., Gelautz, M., Beuschel, R.M.
Format: Article
Language:English
Subjects:
Application software
Circuit testing
Computer architecture
Computer programs
Computer simulation
Decoders
Decoding
Design exploration
Design methodology
Estimating
H264 decoder
Hardware
Mathematical models
Multicore processing
parallel architectures
Software
Software performance
Software testing
Space exploration
Splitting
Studies
video processing
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Summary:In this paper, we introduce a high-level simulation methodology for the modeling of multicore video processing architectures. This method allows design space explorations of parallel video processing applications (VPAs). It is used to test the performance of running a VPA on arbitrary virtual hardware and software configurations. The method represents an alternative to performing a "complete" decoder implementation on a field-programmable gate array or an application-specific integrated circuit. The use of our method, therefore, yields the advantage of being considerably more time, labor, and cost efficient. As an application, we use our method for designing a parallel H.264 decoder targeting 720 p 25 resolution at bit-rates up to 50 Mb/s. Starting from a single-core decoder implementation, we use our simulator for estimating the performance gain when using a multicore architecture. We then detect the major performance bottlenecks in this multicore system and perform additional decoder splittings accordingly until we reach the targeted requirements. The use of functional splitting (i.e., pipelining) and data-parallel processing is demonstrated. The final H.264 decoder architecture is capable of fulfilling our performance requirements.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2009.2031523