Improvement method of the machine-model ESD robustness for a smart power IC

The failure behavior of the smart power IC using a 0.35 mum bipolar-CMOS-DMOS was investigated, and the major ESD failure spots were found at the corner of the guard-ring structure and the high-voltage transistor, which is connected between the different power domains (Vdd-Vcc). The mechanism of the...

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Bibliographic Details
Main Authors: Jong-Kyu Song, Dae-Woo Kim, Jong-Min Kim, Won-Young Jung, Jae-Kyung Wee
Format: Conference Proceeding
Language:English
Subjects:
Electrostatic discharge
Failure analysis
Integrated circuit modeling
Power engineering and energy
Power integrated circuits
Protection
RLC circuits
Robustness
Stress
Testing
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Summary:The failure behavior of the smart power IC using a 0.35 mum bipolar-CMOS-DMOS was investigated, and the major ESD failure spots were found at the corner of the guard-ring structure and the high-voltage transistor, which is connected between the different power domains (Vdd-Vcc). The mechanism of these failures is investigated by the T-CAD simulation, and the method to improve the Machine Model (MM) Robustness is provided. To improve the MM level, the power rail was modified for blocking an unexpected ESD current path using the cost-effective metal revision. This increased MM ESD robustness significantly from 150V to 230V.
ISSN:1946-1542
1946-1550
DOI:10.1109/IPFA.2009.5232598