Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate

We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively,...

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Bibliographic Details
Main Authors: Jyi-Tsong Lin, Chih-Hao Kuo, Tai-Yi Lee, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, Chih-Hung Sun, Hsien-Nan Chiu
Format: Conference Proceeding
Language:English
Subjects:
CMOS process
Double-gate FETs
Etching
Lithography
MOSFET circuits
Parasitic capacitance
Silicon on insulator technology
Substrates
Transconductance
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Summary:We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional VMOS.
ISSN:1946-1542
DOI:10.1109/IPFA.2009.5232696