A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer

Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the propos...

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Bibliographic Details
Published in:IEEE electron device letters 2009-10, Vol.30 (10), p.1093-1095
Main Authors: Luo, Xiaorong, Lei, Tianfei, Wang, Yuangang, Gao, Huanmei, Fang, Jian, Qiao, Ming, Zhang, Wei, Deng, Hao, Zhang, Bo, Li, Zhaoji, Xiao, Zhiqiang, Chen, Zhengcai, Xu, Jing
Format: Article
Language:English
Subjects:
Applied sciences
Biomembranes
Breakdown
Circuits
Compatibility
Compound structure devices
Depletion
Design. Technologies. Operation analysis. Testing
Devices
Dielectric devices
Dielectric substrates
Drift
Electric fields
Electrical engineering. Electrical power engineering
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Etching
Exact sciences and technology
High-voltage techniques
Integrated circuits
Isolation technology
Oxides
Power electronics, power supplies
Power semiconductor devices
Region 8
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon on insulator technology
silicon-on-insulator (SOI) technology
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Summary:Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 V/mum in the conventional devices on p-SOI layer to 27 V/mum, resulting in enhancement of the BOX electric field EI from 30 to 82 V/mum. Moreover, holes located between the depleted n-islands help to increase EI as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2009.2028249