The implementation and design methodology of a quad-core version Godson-3 microprocessor

Godson-3A is a quad-core version of Godson-3 series which is a 174 mm 2 , 425 million transistors chip fabricated using 65 nm CMOS LP/GP process technology. It can be running at 1 GHz with less than 15 W power consumption. Large scale, high frequency, low power and tight time schedule make great cha...

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Bibliographic Details
Main Authors: Baoxia Fan, Liang Yang, Zhuo Gao, Feng Zhang, Ru Wang
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Chip scale packaging
CMOS process
CMOS technology
Design methodology
Energy consumption
Frequency
Large-scale systems
Microprocessors
Processor scheduling
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Description
Summary:Godson-3A is a quad-core version of Godson-3 series which is a 174 mm 2 , 425 million transistors chip fabricated using 65 nm CMOS LP/GP process technology. It can be running at 1 GHz with less than 15 W power consumption. Large scale, high frequency, low power and tight time schedule make great challenges in the chip design. To overcome these challenges, a design methodology based on ASIC combining with semi-custom (manual placement and routing using standard cells) and full-custom is adopted. This paper describes the implementation of Godson-3A microprocessor and the methodology used in the chip design.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2009.5235942