Performance of CNFET SRAM cells under diameter variation corners

In this paper three carbon nanotube FET based static memory cells are compared on read and write delays, energy consumption, and performance under diameter variation corners. The carbon nanotube FET is currently considered to be the possible ldquobeyond CMOSrdquo device due to its1-D transport prope...

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Bibliographic Details
Main Authors: Zhe Zhang, Yanmin Liu, Nyathi, J., Delgado-Frias, J.G.
Format: Conference Proceeding
Language:English
Subjects:
Carbon nanotubes
CMOS technology
CNTFETs
Delay
FinFETs
MOSFETs
Power dissipation
Random access memory
Read-write memory
Semiconductivity
Online Access:Request full text
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Summary:In this paper three carbon nanotube FET based static memory cells are compared on read and write delays, energy consumption, and performance under diameter variation corners. The carbon nanotube FET is currently considered to be the possible ldquobeyond CMOSrdquo device due to its1-D transport properties that include low carrier scattering and ballistic transport. The memory cells are classified by their transistor count (6-, 7- and 8-transistor cell.) Under a nominal diameter of 1.51 nm, the 8-T cell has the lowest delay and energy consumption of 3.7 ps and 0.348 fJ, respectively. Simulations with transistor diameter variations show that small n-type device diameters result in significantly slow read and write delays. The 8-transistor cell dissipates the least energy when the transistor diameters range from 1.369 nm to 1.659 nm.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2009.5236035