A 0.1 mm ^ , Wide Bandwidth Continuous-Time \Sigma\Delta ADC Based on a Time Encoding Quantizer in 0.13 \mu m CMOS

• Published in: IEEE journal of solid-state circuits 2009-10, Vol.44 (10), p.2745-2754
• Main Authors: Prefasi, E., Hernandez, L., Paton, S., Wiesbauer, A., Gaggl, R., Pun, E.
• Format: Article
• Language: English
• Subjects: Analog-to-digital conversion; Bandwidth; Circuits; Computed tomography; continuous-time filters; Delta-sigma modulation; Energy resolution; Filters; Frequency; low-pass filters; low-voltage design; Prototypes; Pulse width modulation; Quantization; sigma-delta modulation; time encoding quantizer
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2027550

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2 ENOB ) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm 2 .