A novel states recovery technique for the TMR softcore processor

The present paper describes a technique for ensuring re- liable softcore processor implementation on SRAM-based field programmable gate arrays (FPGAs), which can handle the effects of single event upsets (SEUs). We propose the triple modular redundancy (TMR) scheme coupled with dynamic partial recon...

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Bibliographic Details
Main Authors: Tanoue, S., Ishida, T., Ichinomiya, Y., Amagasaki, M., Kuga, M., Sueyoshi, T.
Format: Conference Proceeding
Language:English
Subjects:
Circuit faults
Electrical fault detection
Error correction
Error correction codes
Field programmable gate arrays
Process design
Random access memory
Redundancy
Single event transient
Single event upset
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Summary:The present paper describes a technique for ensuring re- liable softcore processor implementation on SRAM-based field programmable gate arrays (FPGAs), which can handle the effects of single event upsets (SEUs). We propose the triple modular redundancy (TMR) scheme coupled with dynamic partial reconfiguration to remove SEUs from the configuration memory of the FPGA. Although the FPGA is subject to SEUs, these errors can be corrected as a result of its reconfigurability. Furthermore, we consider the synchronization after a partial reconfiguration using an interrupt process of an RTOS. Experimental results reveal that one faulty softcore processor is recovered and synchronized with the other softcore processors. The present study demonstrates that a softcore processor can recover from an SEU using the proposed dynamic partial reconfiguration and the synchronization process.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2009.5272423