Efficient methodologies to study the signal integrity of multi Gb/s interconnects and full system EMC

This paper presents modern simulation techniques for the signal integrity (SI) of high speed interconnects (HSI) and full system EMC analysis. Partial element equivalent circuit (PEEC) is effectively use for EM and SPICE simulation. Different test boards are studied and results are validated by comp...

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Bibliographic Details
Main Authors: Ciccomancini Scogna, A., Johns, D.P.
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Circuit simulation
Circuit testing
Electromagnetic compatibility
Equivalent circuits
Guidelines
Integrated circuit interconnections
Signal analysis
SPICE
Transmission line matrix methods
Online Access:Request full text
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Description
Summary:This paper presents modern simulation techniques for the signal integrity (SI) of high speed interconnects (HSI) and full system EMC analysis. Partial element equivalent circuit (PEEC) is effectively use for EM and SPICE simulation. Different test boards are studied and results are validated by comparing multiple numerical methods. Guidelines for a full channel analysis are also provided and system level EMC is also investigated by means of transmission line matrix (TLM) method.
ISSN:2158-110X
2158-1118
DOI:10.1109/ISEMC.2009.5284557