A low-power, high-speed CMOS/CML 16:1 serializer

This paper presents a low power CMOS/CML 16:1 serializer for optical data transmission systems. The serializer comprises a 16:N CMOS multiplexer, a CMOS to CML data converter, a N:1 CML multiplexer, a CML to CMOS clock converter and clock dividers. The serializer was implemented in two technologies:...

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Bibliographic Details
Main Authors: Tondo, D.F., Lopez, R.R.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS logic circuits
CMOS process
CMOS technology
High speed optical techniques
Jitter
Multiplexing
Optical signal processing
Optical transmitters
Transceivers
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Summary:This paper presents a low power CMOS/CML 16:1 serializer for optical data transmission systems. The serializer comprises a 16:N CMOS multiplexer, a CMOS to CML data converter, a N:1 CML multiplexer, a CML to CMOS clock converter and clock dividers. The serializer was implemented in two technologies: fabricated in 65-nm CMOS process and a total area of 110 mum times 390 mum, consumes 106 mW from 1/1.8-V supplies, designed in 45-nm CMOS process and a total area of 140 mum times 360 mum, consumes 50 mW from 0.9/1.2-V supplies. In both cases, simulated DDJ is less than 3 ps under worst case conditions. Advantages of using static CMOS and CML topologies together for high-speed digital signals are discussed. A design method for avoiding timing issues is presented.
DOI:10.1109/EAMTA.2009.5288894