Accelerating SPICE Model-Evaluation using FPGAs

• Main Authors: Kapre, N., DeHon, A.
• Format: Conference Proceeding
• Language: English
• Subjects: Acceleration; Analog Circuit Simulator; Circuit simulation; Computational modeling; Computer architecture; Coupling circuits; Field programmable gate arrays; Floating-Point; Integrated circuit interconnections; Loop Unrolling; Microprocessors; Parallel processing; Spatial Computation; SPICE; VLIW Scheduling
• DOI: 10.1109/FCCM.2009.14

Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SPICE model-evaluation. Model-evaluation is a key component of the SPICE circuit simulator and it is characterized by large irregular floating-point compute graphs. We show how to exploit the parallelism available in these graphs on single-FPGA designs with a low-overhead VLIW-scheduled architecture. Our architecture uses spatial floating-point operators coupled to local high-bandwidth memories and interconnected by a time-shared network. We retime operation inputs in the model-evaluation to allow independent scheduling of computation and communication. With this approach, we demonstrate speedups of 2-18times over a dual-core 3 GHz Intel Xeon 5160 when using a Xilinx Virtex 5 LX330T for a variety of SPICE device models.