Automatic functional model validation between SPICE and Verilog

This paper outlines the development of a validation methodology suitable for testing and qualification of ASIC libraries. In particular this paper outlines a method which uses SPICE models in conjunction with Verilog models to validate the functionality of a Verilog library.

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Bibliographic Details
Main Authors: Naum, M.C., Inoue, Y.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Automatic testing
Counting circuits
Current supplies
Design automation
Hardware design languages
Libraries
Process design
SPICE
Test pattern generators
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Description
Summary:This paper outlines the development of a validation methodology suitable for testing and qualification of ASIC libraries. In particular this paper outlines a method which uses SPICE models in conjunction with Verilog models to validate the functionality of a Verilog library.
ISSN:0197-2618
2576-702X
DOI:10.1109/IAS.1995.530422