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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insula...
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| creator | Chen, C.L. Yost, D.-R. Knecht, J.M. Chapman, D.C. Oakley, D.C. Mahoney, L.J. Donnelly, J.P. Soares, A.M. Suntharalingam, V. Berger, R. Bolkhovsky, V. Hu, W. Wheeler, B.D. Keast, C.L. Shaver, D.C. |
| description | In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 times 1024 diode array with 8-mum pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si. |
| doi_str_mv | 10.1109/3DIC.2009.5306556 |
| format | conference_proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9781424445110 |
| ispartof | 2009 IEEE International Conference on 3D System Integration, 2009, p.1-4 |
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| language | eng |
| recordid | cdi_ieee_primary_5306556 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Diodes Fabrication III-V semiconductor materials Image sensors Indium gallium arsenide Indium phosphide Integrated circuit interconnections Sensor arrays Silicon on insulator technology Wafer bonding |
| title | Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits |
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