Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm2 ADC with binary tree structure

A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bits resolution, using a binary tree structure is presented which needs very low silicon area and relatively low power consumption for its implementation. The sampling rate of the 12-bit ADC exceeds 140MS/...

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Bibliographic Details
Main Authors: Petrellis, N., Birbas, M., Kikidis, J., Birbas, A.
Format: Conference Proceeding
Language:English
Subjects:
Analog-digital conversion
Binary trees
Circuits
Costs
Energy consumption
Low voltage
Pipelines
Sampling methods
Silicon
Ultra wideband technology
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Description
Summary:A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bits resolution, using a binary tree structure is presented which needs very low silicon area and relatively low power consumption for its implementation. The sampling rate of the 12-bit ADC exceeds 140MS/s and requires only 0.12 mm 2 of area making it appropriate for ultra wideband time-interleaved parallel ADC architectures.
ISSN:1946-0740
1946-0759
DOI:10.1109/ETFA.2009.5347207