A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance systolic hardware architecture for 1BT based ME...

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Bibliographic Details
Main Authors: Akin, A., Dogan, Y., Hamzaoglu, I.
Format: Conference Proceeding
Language:English
Subjects:
Computational complexity
Computer architecture
Design engineering
Design methodology
Digital systems
Field programmable gate arrays
Filters
Hardware design languages
Motion estimation
Video compression
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Summary:Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance systolic hardware architecture for 1BT based ME. The proposed hardware performs full search ME for 4 Macroblocks in parallel and it is the fastest 1BT based ME hardware reported in the literature. In addition, it uses less on-chip memory than the previous 1BT based ME hardware by using a novel data reuse scheme and memory organization. The proposed hardware is implemented in Verilog HDL. It consumes %34 of the slices in a Xilinx XC2VP30-7 FPGA. It works at 115 MHz in the same FPGA and is capable of processing 50 1920 × 1080 full High Definition frames per second. Therefore, it can be used in consumer electronics products that require real-time video processing or compression.
DOI:10.1109/DSD.2009.230