Robustness Check for Multiple Faults Using Formal Techniques

Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft errors can be taken on all design stages, e.g. the architectural level, algorithmic level, or on the layout level. Whether th...

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Bibliographic Details
Main Authors: Frehse, S., Fey, G., Suflow, A., Drechsler, R.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Circuit faults
Computer architecture
Computer errors
Design methodology
Digital systems
Error correction codes
formal verification
multiple event upsets
Robustness
Single event upset
soft errors
Very large scale integration
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Summary:Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft errors can be taken on all design stages, e.g. the architectural level, algorithmic level, or on the layout level. Whether the final implementation contains flaws or really provides robustness to soft errors remains to be checked. Here, we propose an approach to formally verify the robustness of a circuit with respect to multiple soft errors. We propose a fault model that prunes the exponentially sized space of multiple soft errors and an algorithm that automatically analyzes a given circuit.
DOI:10.1109/DSD.2009.218