Deep sub-micron and self-aligned flatband III-V MOSFETs

In conclusion, this paper reports a number of significant developments in III-V MOSFET devices. Retaining a subthreshold slope of 60-70 mV/decade for gate lengths down to 100 nm with an EOT of 3.4 nm shows for the first time that the flatband mode device architecture is tolerant to short channel eff...

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Bibliographic Details
Main Authors: Hill, R.J.W., Li, X., Zhou, H., Macintyre, D.S., Thoms, S., Holland, M.C., Longo, P., Moran, D.A.J., Craven, A.J., Stanley, C.R., Asenov, A., Droopad, R., Passlack, M., Thayne, I.G.
Format: Conference Proceeding
Language:English
Subjects:
Dielectrics
Displays
Geometry
Gold
III-V semiconductor materials
Interface states
MOSFETs
Nanoelectronics
Silicon
Very large scale integration
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Summary:In conclusion, this paper reports a number of significant developments in III-V MOSFET devices. Retaining a subthreshold slope of 60-70 mV/decade for gate lengths down to 100 nm with an EOT of 3.4 nm shows for the first time that the flatband mode device architecture is tolerant to short channel effects. In addition, a generic silicon compatible process flow for the realization of fully self-aligned III-V MOSFETs has been demonstrated and shown capable of realizing 100 nm gate length enhancement mode devices.
ISSN:1548-3770
2640-6853
DOI:10.1109/DRC.2009.5354900