Efficient Methods for Large Resistor Networks

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2010-01, Vol.29 (1), p.28-39
• Main Authors: Rommes, Joost, Schilders, Wil H. A.
• Format: Article
• Language: English
• Subjects: Algorithm design and analysis; Approximate minimum degree; Cholesky decomposition; Circuit simulation; Computational modeling; Computer networks; electro static discharge analysis; Electrostatic discharge; graph algorithms; Immune system; Integrated circuit interconnections; large-scale systems; model order reduction; parasitic extraction; path resistance; resistor networks; Resistors; Semiconductor diodes; strongly connected components; two-connected components; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2009.2034402

Large resistor networks arise during the design of very-large-scale integration chips as a result of parasitic extraction and electro static discharge analysis. Simulating these large parasitic resistor networks is of vital importance, since it gives an insight into the functional and physical performance of the chip. However, due to the increasing amount of interconnect and metal layers, these networks may contain millions of resistors and nodes, making accurate simulation time consuming or even infeasible. We propose efficient algorithms for three types of analysis of large resistor networks: 1) computation of path resistances; 2) computation of resistor currents; and 3) reduction of resistor networks. The algorithms are exact, orders of magnitude faster than conventional approaches, and enable simulation of very large networks.