Efficient Design of Digital up Converter for WCDMA in FPGA Using System Generator

In this paper, we propose the design and implementation of the digital up converter (DUC) on xilinx FPGA for WCDMA. To shorten the design cycle and increase the design productivity, a powerful system design tool, Xilinx System Generator, is adopted. Submodules of the DUC, such as the RRC filter and...

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Main Authors: Lin, Fei-yu, Qiao, Wei-ming, Jiao, Xi-xiang, Jing, Lan, Ma, Yun-hai
Format: Conference Proceeding
Language:English
Subjects:
Baseband
Downlink
Field programmable gate arrays
Finite impulse response filter
Frequency conversion
Interpolation
MATLAB
Multiaccess communication
Pulse shaping methods
Radio transmitters
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Qiao, Wei-ming
Jiao, Xi-xiang
Jing, Lan
Ma, Yun-hai
description In this paper, we propose the design and implementation of the digital up converter (DUC) on xilinx FPGA for WCDMA. To shorten the design cycle and increase the design productivity, a powerful system design tool, Xilinx System Generator, is adopted. Submodules of the DUC, such as the RRC filter and the half-band filters, are designed using MATLAB FDATool and Xilinx FIR Compiler. The DDS submodule is produced by Xilinx DDS Compiler. Using Vitex-5 DSP48E slices, the complex multiplier operation frequency reaches 368.64 MHz.The DUC needs to be pulse shaped and up sampled the baseband signal by a factor of 16 to 61.44 MHz to meet the WCDMA specifications. Finally, we have implemented the DUC design on Xilinx XC5VSX50T FPGA device.
doi_str_mv 10.1109/ICIECS.2009.5366979
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subjects Baseband
Downlink
Field programmable gate arrays
Finite impulse response filter
Frequency conversion
Interpolation
MATLAB
Multiaccess communication
Pulse shaping methods
Radio transmitters
title Efficient Design of Digital up Converter for WCDMA in FPGA Using System Generator
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