An I/Q channel 12-bit 200MS/s CMOS DAC with three stage decoders for wireless communication

This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current m...

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Bibliographic Details
Main Authors: Yunhua Yu, Haitao Shi, Weining Ni
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS analog integrated circuits
CMOS digital integrated circuits
CMOS mixed integrated circuit
current-steering
DAC
Decoding
Energy consumption
Linearity
Q 2 Random Walk
Switches
Symmetric matrices
Wireless communication
Wireless LAN
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Summary:This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q 2 random walk strategy. A voltage limiter circuit that limits the switching voltage magnitude is designed to reduce the coupling effect from the control signal to the load and improve the dynamic performance.
DOI:10.1109/WCSP.2009.5371403