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An I/Q channel 12-bit 200MS/s CMOS DAC with three stage decoders for wireless communication
This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current m...
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| creator | Yunhua Yu Haitao Shi Weining Ni |
| description | This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q 2 random walk strategy. A voltage limiter circuit that limits the switching voltage magnitude is designed to reduce the coupling effect from the control signal to the load and improve the dynamic performance. |
| doi_str_mv | 10.1109/WCSP.2009.5371403 |
| format | conference_proceeding |
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The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q 2 random walk strategy. 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The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q 2 random walk strategy. A voltage limiter circuit that limits the switching voltage magnitude is designed to reduce the coupling effect from the control signal to the load and improve the dynamic performance.</description><subject>Clocks</subject><subject>CMOS analog integrated circuits</subject><subject>CMOS digital integrated circuits</subject><subject>CMOS mixed integrated circuit</subject><subject>current-steering</subject><subject>DAC</subject><subject>Decoding</subject><subject>Energy consumption</subject><subject>Linearity</subject><subject>Q 2 Random Walk</subject><subject>Switches</subject><subject>Symmetric matrices</subject><subject>Wireless communication</subject><subject>Wireless LAN</subject><isbn>9781424448562</isbn><isbn>1424448565</isbn><isbn>9781424456680</isbn><isbn>1424456681</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpFUE1Lw0AUXJGCWvsDxMv-gTRvv3ePJWottFRpwYOHssm-2JU2kWxE_PdGLDiXYZh5j2EIuWEwZQxc_lJsnqYcwE2VMEyCOCMTZyyTXEqltYXzfy2t0nxErn7jDpRWcEEmKb3DAKm4cOaSvM4ausifabX3TYMHynhWxp4OJ6tNnmixWm_o3aygX7Hf037fIdLU-zekAas2YJdo3XaD2-EBU6JVezx-NrHyfWybazKq_SHh5MRjsn243xaP2XI9XxSzZRYd9BkOxYIPPFhtZBmYC8xwAdbJ0jrwAgMLTDstnBSmFsFDpQzjFitdgtdWjMnt39uIiLuPLh599707zSN-APvHU10</recordid><startdate>200911</startdate><enddate>200911</enddate><creator>Yunhua Yu</creator><creator>Haitao Shi</creator><creator>Weining Ni</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200911</creationdate><title>An I/Q channel 12-bit 200MS/s CMOS DAC with three stage decoders for wireless communication</title><author>Yunhua Yu ; Haitao Shi ; Weining Ni</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-e565dad2d8674bd19d17230894b890a3ed1d169639437f3da0c57128ec6b0a683</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Clocks</topic><topic>CMOS analog integrated circuits</topic><topic>CMOS digital integrated circuits</topic><topic>CMOS mixed integrated circuit</topic><topic>current-steering</topic><topic>DAC</topic><topic>Decoding</topic><topic>Energy consumption</topic><topic>Linearity</topic><topic>Q 2 Random Walk</topic><topic>Switches</topic><topic>Symmetric matrices</topic><topic>Wireless communication</topic><topic>Wireless LAN</topic><toplevel>online_resources</toplevel><creatorcontrib>Yunhua Yu</creatorcontrib><creatorcontrib>Haitao Shi</creatorcontrib><creatorcontrib>Weining Ni</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yunhua Yu</au><au>Haitao Shi</au><au>Weining Ni</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An I/Q channel 12-bit 200MS/s CMOS DAC with three stage decoders for wireless communication</atitle><btitle>2009 International Conference on Wireless Communications & Signal Processing</btitle><stitle>WCSP</stitle><date>2009-11</date><risdate>2009</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>9781424448562</isbn><isbn>1424448565</isbn><eisbn>9781424456680</eisbn><eisbn>1424456681</eisbn><abstract>This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q 2 random walk strategy. A voltage limiter circuit that limits the switching voltage magnitude is designed to reduce the coupling effect from the control signal to the load and improve the dynamic performance.</abstract><pub>IEEE</pub><doi>10.1109/WCSP.2009.5371403</doi><tpages>4</tpages></addata></record> |
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| identifier | ISBN: 9781424448562 |
| ispartof | 2009 International Conference on Wireless Communications & Signal Processing, 2009, p.1-4 |
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| language | eng |
| recordid | cdi_ieee_primary_5371403 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks CMOS analog integrated circuits CMOS digital integrated circuits CMOS mixed integrated circuit current-steering DAC Decoding Energy consumption Linearity Q 2 Random Walk Switches Symmetric matrices Wireless communication Wireless LAN |
| title | An I/Q channel 12-bit 200MS/s CMOS DAC with three stage decoders for wireless communication |
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