Dynamic Partial Reconfigurable Embedded System to Achieve Hardware Flexibility Using 8051 Based RTOS on Xilinx FPGA

Field Programmable Gate Arrays (FPGAs) are increasingly being used for many systems and efficient System-on-a-Chip (SOC) designs. Hence, dynamic partial self reconfiguration (DPSR) of the FPGA can be regarded as one of essentials of making hardware flexible and achieving power efficiency and optimiz...

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Bibliographic Details
Main Authors: Zalke, J.B., Pandey, S.K.
Format: Conference Proceeding
Language:English
Subjects:
Control systems
Dynamic partial reconfiguration
Educational institutions
Embedded computing
Embedded system
Energy consumption
Field programmable gate arrays
Hardware
Power engineering and energy
self reconfiguration
Telecommunication computing
Telecommunication control
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Summary:Field Programmable Gate Arrays (FPGAs) are increasingly being used for many systems and efficient System-on-a-Chip (SOC) designs. Hence, dynamic partial self reconfiguration (DPSR) of the FPGA can be regarded as one of essentials of making hardware flexible and achieving power efficiency and optimizing area too. This paper presents an approach for dynamic partial self-reconfiguration that enables FPGAs to reconfigure itself dynamically and partially under the control of an external processor. The reconfiguration process is accomplished without an internal configuration access port (ICAP), which should be used either with Micro Blaze soft core or with PowerPC hard core using HWICAP core for the On-Chip Peripheral Bus (OPB). It can also be used for any other FPGA architectures, such as Virtex-II (Pro), Virtex-4, Virtex-5, etc.
DOI:10.1109/ACT.2009.174