A Low-Power Skew Tolerant Domino Digit Serial Multiplier

Demands for high speed low power VLSI have been pushing the development of aggressive design methodologies to reduce power consumption drastically and reduce cycle times. The objective of this research paper is to design a connection between digit-serial computing and skew tolerant domino circuit an...

Full description

Saved in:
Bibliographic Details
Main Authors: Akkamahadevi, D.H., Nataraj Urs, H.D.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Clocks
CMOS logic circuits
Digital signal processing
Energy consumption
Frequency
Leakage current
Logic circuits
Signal processing algorithms
Telecommunication computing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 590
container_issue
container_start_page 588
container_title
container_volume
creator Akkamahadevi, D.H.
Nataraj Urs, H.D.
description Demands for high speed low power VLSI have been pushing the development of aggressive design methodologies to reduce power consumption drastically and reduce cycle times. The objective of this research paper is to design a connection between digit-serial computing and skew tolerant domino circuit and apply it to the design of signed multipliers with reduction in number of MOS transistors used. A 16-bit signed multiplier having a digit size of 4 bits is naturally and efficiently mapped into a skew-tolerant domino implementation using 4 overlapping clock phases. To reduce the power a 14T CMOS 1-bit adder cell is used.
doi_str_mv 10.1109/ACT.2009.149
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5376474</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5376474</ieee_id><sourcerecordid>5376474</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-66a8e42c550b7fb8611fd87f82a916ba4efa9a010d63c94a6f8ed64285f4564a3</originalsourceid><addsrcrecordid>eNotzLtOwzAUAFAjhAQt3dhY_AMJflxf22OU8pKCQGr2ymmukUXaVE5QxN8zwHS2w9idFKWUwj9UdVsqIXwpwV-wlbDojfbS2Eu2kqAAjFYSr9lmmlInFFo0xtob5irejEvxMS6U-e6LFt6OA-Vwmvl2PKbTyLfpM818RzmFgb99D3M6D4nyLbuKYZho8--atU-Pbf1SNO_Pr3XVFMmLuUAMjkAdjBGdjZ1DKWPvbHQqeIldAIrBByFFj_rgIWB01CMoZyIYhKDX7P6vTUS0P-d0DPlnb7RFsKB_AadyROg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Low-Power Skew Tolerant Domino Digit Serial Multiplier</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Akkamahadevi, D.H. ; Nataraj Urs, H.D.</creator><creatorcontrib>Akkamahadevi, D.H. ; Nataraj Urs, H.D.</creatorcontrib><description>Demands for high speed low power VLSI have been pushing the development of aggressive design methodologies to reduce power consumption drastically and reduce cycle times. The objective of this research paper is to design a connection between digit-serial computing and skew tolerant domino circuit and apply it to the design of signed multipliers with reduction in number of MOS transistors used. A 16-bit signed multiplier having a digit size of 4 bits is naturally and efficiently mapped into a skew-tolerant domino implementation using 4 overlapping clock phases. To reduce the power a 14T CMOS 1-bit adder cell is used.</description><identifier>ISBN: 1424453216</identifier><identifier>ISBN: 9781424453214</identifier><identifier>EISBN: 0769539157</identifier><identifier>EISBN: 9780769539157</identifier><identifier>DOI: 10.1109/ACT.2009.149</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Clocks ; CMOS logic circuits ; Digital signal processing ; Energy consumption ; Frequency ; Leakage current ; Logic circuits ; Signal processing algorithms ; Telecommunication computing</subject><ispartof>2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies, 2009, p.588-590</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5376474$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5376474$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Akkamahadevi, D.H.</creatorcontrib><creatorcontrib>Nataraj Urs, H.D.</creatorcontrib><title>A Low-Power Skew Tolerant Domino Digit Serial Multiplier</title><title>2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies</title><addtitle>ACT</addtitle><description>Demands for high speed low power VLSI have been pushing the development of aggressive design methodologies to reduce power consumption drastically and reduce cycle times. The objective of this research paper is to design a connection between digit-serial computing and skew tolerant domino circuit and apply it to the design of signed multipliers with reduction in number of MOS transistors used. A 16-bit signed multiplier having a digit size of 4 bits is naturally and efficiently mapped into a skew-tolerant domino implementation using 4 overlapping clock phases. To reduce the power a 14T CMOS 1-bit adder cell is used.</description><subject>Capacitance</subject><subject>Clocks</subject><subject>CMOS logic circuits</subject><subject>Digital signal processing</subject><subject>Energy consumption</subject><subject>Frequency</subject><subject>Leakage current</subject><subject>Logic circuits</subject><subject>Signal processing algorithms</subject><subject>Telecommunication computing</subject><isbn>1424453216</isbn><isbn>9781424453214</isbn><isbn>0769539157</isbn><isbn>9780769539157</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotzLtOwzAUAFAjhAQt3dhY_AMJflxf22OU8pKCQGr2ymmukUXaVE5QxN8zwHS2w9idFKWUwj9UdVsqIXwpwV-wlbDojfbS2Eu2kqAAjFYSr9lmmlInFFo0xtob5irejEvxMS6U-e6LFt6OA-Vwmvl2PKbTyLfpM818RzmFgb99D3M6D4nyLbuKYZho8--atU-Pbf1SNO_Pr3XVFMmLuUAMjkAdjBGdjZ1DKWPvbHQqeIldAIrBByFFj_rgIWB01CMoZyIYhKDX7P6vTUS0P-d0DPlnb7RFsKB_AadyROg</recordid><startdate>200912</startdate><enddate>200912</enddate><creator>Akkamahadevi, D.H.</creator><creator>Nataraj Urs, H.D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200912</creationdate><title>A Low-Power Skew Tolerant Domino Digit Serial Multiplier</title><author>Akkamahadevi, D.H. ; Nataraj Urs, H.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-66a8e42c550b7fb8611fd87f82a916ba4efa9a010d63c94a6f8ed64285f4564a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Capacitance</topic><topic>Clocks</topic><topic>CMOS logic circuits</topic><topic>Digital signal processing</topic><topic>Energy consumption</topic><topic>Frequency</topic><topic>Leakage current</topic><topic>Logic circuits</topic><topic>Signal processing algorithms</topic><topic>Telecommunication computing</topic><toplevel>online_resources</toplevel><creatorcontrib>Akkamahadevi, D.H.</creatorcontrib><creatorcontrib>Nataraj Urs, H.D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library Online</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Akkamahadevi, D.H.</au><au>Nataraj Urs, H.D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Low-Power Skew Tolerant Domino Digit Serial Multiplier</atitle><btitle>2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies</btitle><stitle>ACT</stitle><date>2009-12</date><risdate>2009</risdate><spage>588</spage><epage>590</epage><pages>588-590</pages><isbn>1424453216</isbn><isbn>9781424453214</isbn><eisbn>0769539157</eisbn><eisbn>9780769539157</eisbn><abstract>Demands for high speed low power VLSI have been pushing the development of aggressive design methodologies to reduce power consumption drastically and reduce cycle times. The objective of this research paper is to design a connection between digit-serial computing and skew tolerant domino circuit and apply it to the design of signed multipliers with reduction in number of MOS transistors used. A 16-bit signed multiplier having a digit size of 4 bits is naturally and efficiently mapped into a skew-tolerant domino implementation using 4 overlapping clock phases. To reduce the power a 14T CMOS 1-bit adder cell is used.</abstract><pub>IEEE</pub><doi>10.1109/ACT.2009.149</doi><tpages>3</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 1424453216
ispartof 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies, 2009, p.588-590
issn
language eng
recordid cdi_ieee_primary_5376474
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Capacitance
Clocks
CMOS logic circuits
Digital signal processing
Energy consumption
Frequency
Leakage current
Logic circuits
Signal processing algorithms
Telecommunication computing
title A Low-Power Skew Tolerant Domino Digit Serial Multiplier
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-23T21%3A15%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Low-Power%20Skew%20Tolerant%20Domino%20Digit%20Serial%20Multiplier&rft.btitle=2009%20International%20Conference%20on%20Advances%20in%20Computing,%20Control,%20and%20Telecommunication%20Technologies&rft.au=Akkamahadevi,%20D.H.&rft.date=2009-12&rft.spage=588&rft.epage=590&rft.pages=588-590&rft.isbn=1424453216&rft.isbn_list=9781424453214&rft_id=info:doi/10.1109/ACT.2009.149&rft.eisbn=0769539157&rft.eisbn_list=9780769539157&rft_dat=%3Cieee_6IE%3E5376474%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i90t-66a8e42c550b7fb8611fd87f82a916ba4efa9a010d63c94a6f8ed64285f4564a3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5376474&rfr_iscdi=true