An area optimized implementation of the Advanced Encryption Standard

Since its adoption as a new encryption standard by NIST, the Advanced Encryption Standard (AES) has become the default choice for various security services in many applications. On the other hand, a straightforward hardware implementation of the AES may not satisfy the tight constraints of several r...

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Bibliographic Details
Main Authors: Kamal, A.A., Youssef, A.M.
Format: Conference Proceeding
Language:English
Subjects:
Cryptography
Design optimization
Hardware
Information systems
Microelectronics
NIST
Polynomials
Radiofrequency identification
RFID tags
Systems engineering and theory
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Summary:Since its adoption as a new encryption standard by NIST, the Advanced Encryption Standard (AES) has become the default choice for various security services in many applications. On the other hand, a straightforward hardware implementation of the AES may not satisfy the tight constraints of several resource limited devices such as radio frequency identification (RFID) tags and tiny sensor networks. In this paper, we explore several area optimization options for the AES. Our area optimized implementation for AES-128 ECB encryption/decryption engine requires 2732 slices of a Xilinx Virtex-II XC2V1000bg575, runs at a maximum clock speed of 98.95 MHz and produces a throughput of up to 29.32 Mbps.
ISSN:2159-1660
DOI:10.1109/ICM.2008.5393805