Efficient implementations of S-box and inverse S-box for AES algorithm

In this paper, improved architectures are proposed for implementation of S-Box and inverse S-Box needed in the Advanced encryption standard (AES) algorithm. These use combinational logic only for implementing SubByte (S-box) and InvSubByte (Inverse S-box). The composite field arithmetic used for imp...

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Bibliographic Details
Main Authors: Rachh, R.R., Anami, B.S., Ananda Mohan, P.V.
Format: Conference Proceeding
Language:English
Subjects:
AES
Computer architecture
Computer science
Cryptography
Data Encryption
Delay
Galois fields
Hardware
Inverse S-Box
Iterative algorithms
Logic
Read only memory
S-Box
Very large scale integration
VLSI architectures
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Description
Summary:In this paper, improved architectures are proposed for implementation of S-Box and inverse S-Box needed in the Advanced encryption standard (AES) algorithm. These use combinational logic only for implementing SubByte (S-box) and InvSubByte (Inverse S-box). The composite field arithmetic used for implementing S-Box in lower-order Galois field (GF) investigated by several authors recently is used as the basis for deriving the proposed architectures. The resulting hardware requirements as well computation time are presented for the proposed designs and compared with previous work.
ISSN:2159-3442
2159-3450
DOI:10.1109/TENCON.2009.5395837