Optimization techniques of on-chip memory system based on UltraSPARC architecture

It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core proc...

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Bibliographic Details
Main Authors: Anwen Huang, Jun Gao, Chaochao Feng, Minxuan Zhang
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Clocks
Costs
Elliptic curve cryptography
Elliptic curves
Hardware
Protection
Random access memory
Registers
System-on-a-chip
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Summary:It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core processor in detail. To get the basic parameters of timing characteristic and area consumption, the primary element of on-chip memory system is simulated by ModelSim and synthesized by Synopsys Design Complier with 90 nm standard cell library. Aimed at the potential limiting factor of improving the performance of memory hierarchy, corresponding optimization techniques of critical elements in memory system are explored finally.
ISSN:2159-2144
2159-2160
DOI:10.1109/PRIMEASIA.2009.5397354