Comparator-based successive folding ADC

A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue pre-charging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that...

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Bibliographic Details
Main Authors: U-Fat Chio, Hou-Lon Choi, Chi-Hang Chan, Si-Seng Wong, Sai-Weng Sin, Seng-Pan U, Martins, R.P.
Format: Conference Proceeding
Language:English
Subjects:
Electronic mail
Energy resolution
Frequency conversion
Laboratories
Output feedback
Quantization
Sampling methods
Silicon compounds
Very large scale integration
Wireless communication
Online Access:Request full text
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Description
Summary:A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue pre-charging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that the ADC obtains a SNDR of 23.7 dB at Nyquist input frequency and consumes 430 ¿W from a 1 V supply in 65 nm CMOS, yielding a FOM of 34 fJ per conversion step.
ISSN:2159-2144
2159-2160
DOI:10.1109/PRIMEASIA.2009.5397434