FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding

Scalable video coding extension of H.264 standard is very suitable for content adaptation and addressing different terminals. However, in various cases it is necessary to perform transcoding in video coding layer requiring tremendous computation and hardware acceleration. In this paper, we present a...

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Bibliographic Details
Main Authors: Guarisco, M., Rabah, H., Berviller, Y., Weber, S., Belkouch, S.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Bit rate
Codecs
Computer architecture
Delay
Discrete cosine transforms
Entropy coding
Hardware
Transcoding
Video coding
Online Access:Request full text
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Summary:Scalable video coding extension of H.264 standard is very suitable for content adaptation and addressing different terminals. However, in various cases it is necessary to perform transcoding in video coding layer requiring tremendous computation and hardware acceleration. In this paper, we present an efficient hardware architecture of a CAVLC codec based on a new method that provides a constant and reduced latency. The presented method calculates the 16 DCT coefficients in parallel. The results of hardware implementation targeting a Xilinx Virtex 5 FPGA are presented.
ISSN:2164-1676
2164-1706
DOI:10.1109/SOCCON.2009.5398004