High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique

A semi-digital clock and data recovery (CDR) circuit implemented in 45 nm SOI process is discussed. The CDR uses two analog phase interpolators to generate in-phase and quadrature-phase clocks to sample incoming data. Due to onchip process variations, the phase interpolators exhibit a nonlinear beha...

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Bibliographic Details
Main Authors: Desai, K., Nagulapalli, R., Krishna, V., Palwai, R., Venkatesan, P.K., Khawshe, V.
Format: Conference Proceeding
Language:English
Subjects:
CDR jitter
Charge pumps
Circuit noise
Clock and data recovery (CDR)
Clocks
Interpolation
Jitter
Phase
Phase locked loops
Protocols
Quantum cascade lasers
Very large scale integration
Voltage-controlled oscillators
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Description
Summary:A semi-digital clock and data recovery (CDR) circuit implemented in 45 nm SOI process is discussed. The CDR uses two analog phase interpolators to generate in-phase and quadrature-phase clocks to sample incoming data. Due to onchip process variations, the phase interpolators exhibit a nonlinear behavior. More so, this behavior is not similar in the two phase interpolators, i.e. there is a mismatch between them. This mismatch gives rise to quadrature error between the two clocks. The impact of this quadrature error on CDR jitter is highlighted for a data rate of 5.0 Gbps (PCIe Gen2 protocol). We propose a novel mechanism to mitigate the effect of this mismatch between the phase interpolators by tracking out the quadrature error. The scheme improves CDR jitter by 29%.
ISSN:1063-9667
2380-6923
DOI:10.1109/VLSI.Design.2010.104