A design methodology for high-performance and low-leakage fixed-point transpose FIR filters

This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-V th CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-V th Multiplication-Addition units by their high-...

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Bibliographic Details
Main Authors: Bekiaris, D., Xydis, S., Economakos, G., Pekmestzi, K.
Format: Conference Proceeding
Language:English
Subjects:
CMOS technology
Design methodology
Electronic mail
Equations
Finite impulse response filter
Libraries
Sleep
Subthreshold current
Threshold voltage
Tunneling
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Summary:This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-V th CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-V th Multiplication-Addition units by their high-V th counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69-25.85% for several clock period constraints, compared to the low-V th FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.
DOI:10.1109/ICECS.2009.5410902