Design challenges in nanometric embedded memories

Embedded memories comprise over half the die area in modern SOC ICs. These circuits enable large gains in performance, however they bring with them many challenges. As CMOS technology scales deep into the nano-metric region the size and density of embedded memories are increasing, both of which resu...

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Bibliographic Details
Main Authors: Rennie, D.J., Shakir, T., Sachdev, M.
Format: Conference Proceeding
Language:English
Subjects:
Circuits and systems
CMOS
CMOS integrated circuits
CMOS memory circuits
CMOS process
CMOS technology
Delay
Joining processes
MOSFETs
Random access memory
scaling
Signal design
soft error
SRAM
variability
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Summary:Embedded memories comprise over half the die area in modern SOC ICs. These circuits enable large gains in performance, however they bring with them many challenges. As CMOS technology scales deep into the nano-metric region the size and density of embedded memories are increasing, both of which result in increased challenges for designers. This paper describes the design challenges intrinsic to the implementation of embedded memories in modern nanometric CMOS processes.
DOI:10.1109/ICSCS.2009.5412617