VLSI implementation of a fairness ATM buffer system

This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that c...

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Bibliographic Details
Main Authors: Nielsen, J.V., Dittman, L., Madsen, J.K., Lassen, P.S.
Format: Conference Proceeding
Language:English
Subjects:
Asynchronous transfer mode
Bandwidth
Buildings
Queueing analysis
Resource management
Robustness
Switches
Telecommunication traffic
Traffic control
Very large scale integration
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Summary:This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component.
DOI:10.1109/ICC.1996.541268