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VLSI implementation of a fairness ATM buffer system
This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that c...
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| container_end_page | 686 vol.2 |
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| container_start_page | 681 |
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| container_volume | 2 |
| creator | Nielsen, J.V. Dittman, L. Madsen, J.K. Lassen, P.S. |
| description | This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component. |
| doi_str_mv | 10.1109/ICC.1996.541268 |
| format | conference_proceeding |
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The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component.</description><identifier>ISBN: 0780332504</identifier><identifier>ISBN: 9780780332508</identifier><identifier>DOI: 10.1109/ICC.1996.541268</identifier><language>eng</language><publisher>IEEE</publisher><subject>Asynchronous transfer mode ; Bandwidth ; Buildings ; Queueing analysis ; Resource management ; Robustness ; Switches ; Telecommunication traffic ; Traffic control ; Very large scale integration</subject><ispartof>Proceedings of ICC/SUPERCOMM '96 - International Conference on Communications, 1996, Vol.2, p.681-686 vol.2</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/541268$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,4036,4037,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/541268$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nielsen, J.V.</creatorcontrib><creatorcontrib>Dittman, L.</creatorcontrib><creatorcontrib>Madsen, J.K.</creatorcontrib><creatorcontrib>Lassen, P.S.</creatorcontrib><title>VLSI implementation of a fairness ATM buffer system</title><title>Proceedings of ICC/SUPERCOMM '96 - International Conference on Communications</title><addtitle>ICC</addtitle><description>This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component.</description><subject>Asynchronous transfer mode</subject><subject>Bandwidth</subject><subject>Buildings</subject><subject>Queueing analysis</subject><subject>Resource management</subject><subject>Robustness</subject><subject>Switches</subject><subject>Telecommunication traffic</subject><subject>Traffic control</subject><subject>Very large scale integration</subject><isbn>0780332504</isbn><isbn>9780780332508</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj0tLw0AUhQdEUGvXgqv5A4l33jPLEnwEUly0uC2T5F4YadKSiYv-eyP1bL4DHxw4jD0JKIWA8FJXVSlCsKXRQlp_wx7AeVBKGtB3bJ3zNyzRxkiv7pn6anY1T8P5iAOOc5zTaeQn4pFTTNOIOfPNfsvbHyKceL7kGYdHdkvxmHH9zxXbvb3uq4-i-Xyvq01TJAu-iOTaSH2P1hknbQhekg4t0dI09QGt7khCZ6MjANst-s9bQ7aTUaoVe76uJkQ8nKc0xOlyuJ5SvyYHQW8</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Nielsen, J.V.</creator><creator>Dittman, L.</creator><creator>Madsen, J.K.</creator><creator>Lassen, P.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>VLSI implementation of a fairness ATM buffer system</title><author>Nielsen, J.V. ; Dittman, L. ; Madsen, J.K. ; Lassen, P.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i608-af7bafdde6757269982f49bff9984fd9e64cf20c6a7f006c82ff49b65f6c2a23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Asynchronous transfer mode</topic><topic>Bandwidth</topic><topic>Buildings</topic><topic>Queueing analysis</topic><topic>Resource management</topic><topic>Robustness</topic><topic>Switches</topic><topic>Telecommunication traffic</topic><topic>Traffic control</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Nielsen, J.V.</creatorcontrib><creatorcontrib>Dittman, L.</creatorcontrib><creatorcontrib>Madsen, J.K.</creatorcontrib><creatorcontrib>Lassen, P.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nielsen, J.V.</au><au>Dittman, L.</au><au>Madsen, J.K.</au><au>Lassen, P.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>VLSI implementation of a fairness ATM buffer system</atitle><btitle>Proceedings of ICC/SUPERCOMM '96 - International Conference on Communications</btitle><stitle>ICC</stitle><date>1996</date><risdate>1996</risdate><volume>2</volume><spage>681</spage><epage>686 vol.2</epage><pages>681-686 vol.2</pages><isbn>0780332504</isbn><isbn>9780780332508</isbn><abstract>This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component.</abstract><pub>IEEE</pub><doi>10.1109/ICC.1996.541268</doi><oa>free_for_read</oa></addata></record> |
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| identifier | ISBN: 0780332504 |
| ispartof | Proceedings of ICC/SUPERCOMM '96 - International Conference on Communications, 1996, Vol.2, p.681-686 vol.2 |
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| language | eng |
| recordid | cdi_ieee_primary_541268 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Asynchronous transfer mode Bandwidth Buildings Queueing analysis Resource management Robustness Switches Telecommunication traffic Traffic control Very large scale integration |
| title | VLSI implementation of a fairness ATM buffer system |
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