Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs

Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an...

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Bibliographic Details
Main Authors: Shimeng Yu, Yuning Zhao, Yuncheng Song, Gang Du, Jinfeng Kang, Ruqi Han, Xiaoyan Liu
Format: Conference Proceeding
Language:English
Subjects:
Autocorrelation
FinFETs
Fluctuations
Leakage current
Microelectronics
MOSFETs
Random sequences
Root mean square
Solid modeling
Threshold voltage
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Summary:Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.
ISSN:2161-4636
2161-4644
DOI:10.1109/SNW.2008.5418481