Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2010-08, Vol.57 (8), p.2053-2065
• Main Authors: Hailong Jiao, Kursun, V
• Format: Article
• Language: English
• Subjects: Active noise reduction; Battery lifetime; Bouncing; Circuit noise; Circuits; CMOS; CMOS technology; Energy consumption; Grounds; idle circuit; intermediate relaxation mode; leakage power consumption; Logic circuits; MOSFETs; Noise; Noise generators; Noise level; Noise reduction; on-chip noise; Power consumption; power gating; Sleep; SLEEP mode; SLEEP to ACTIVE mode transition; Subthreshold current
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2010.2041505

Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the ground-bouncing-noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual lines to the real ground distribution network during the SLEEP to ACTIVE mode transitions. The dependence of ground bouncing noise on the sleep transistor size and temperature is characterized with different power-gating structures. The peak amplitude of ground bouncing noise is reduced by up to 76.62% with the noise-aware techniques without sacrificing the savings in leakage power consumption as compared with standard MTCMOS circuits in a 90-nm CMOS technology.