Benefits of vertically stacked integrated circuits for sequential logic

Future demands for performance of electronic systems will push the development of three-dimensional (3-D) packaging technologies. Up to now 3-D stacking techniques are just used to realize high density memory modules. In this paper we investigate problems and solutions of sequential logic circuit de...

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Main Authors: Reber, M., Tielert, R.
Format: Conference Proceeding
Language:English
Subjects:
Controllability
Feedback loop
Hardware
Multiplexing
Observability
Registers
Semiconductor device measurement
Sequential circuits
Testing
Wiring
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Tielert, R.
description Future demands for performance of electronic systems will push the development of three-dimensional (3-D) packaging technologies. Up to now 3-D stacking techniques are just used to realize high density memory modules. In this paper we investigate problems and solutions of sequential logic circuit design for vertically stacked integrated circuits (VIC). We analyze a test strategy and a 3-D placement tool for VICs that allows us to generate globally optimized circuit layouts by a 3-D arrangement of gates. Our focus is on test overhead obtained by the proposed test strategy for VICs and the reduction of wiring space attained by 3-D routing. Additionally we discuss the effect of our 3-D placement procedure on fault coverage. The results obtained using this procedure in different circuit layouts for 3-D circuits are compared to single chip solutions.
doi_str_mv 10.1109/ISCAS.1996.541915
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identifier ISBN: 9780780330733
ispartof 1996 IEEE International Symposium on Circuits and Systems (ISCAS), 1996, Vol.4, p.121-124 vol.4
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language eng
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Controllability
Feedback loop
Hardware
Multiplexing
Observability
Registers
Semiconductor device measurement
Sequential circuits
Testing
Wiring
title Benefits of vertically stacked integrated circuits for sequential logic
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