Low-power class-AB CMOS OTA with high slew-rate

In this paper, a novel low-power class-AB CMOS OTA with high slew-rate is presented. The proposed OTA is based on class-AB input stage using a novel adaptive-biasing. The proposed OTA designed using a standard 0.18-um CMOS technology indicates that rising and falling slew-rates of +4.92 V/¿S and -5....

Full description

Saved in:
Bibliographic Details
Main Authors: Ah-Reum Kim, Hyoung-Rae Kim, Yoon-Suk Park, Yoon-Kyung Choi, Bai-Sun Kong
Format: Conference Proceeding
Language:English
Subjects:
adaptive biasing
Capacitance
Class-AB OTA
CMOS analog circuit
CMOS technology
Design engineering
Energy consumption
Equations
Feedback circuits
low power
Silicon
slew rate enhancement
Tail
Transconductance
Voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, a novel low-power class-AB CMOS OTA with high slew-rate is presented. The proposed OTA is based on class-AB input stage using a novel adaptive-biasing. The proposed OTA designed using a standard 0.18-um CMOS technology indicates that rising and falling slew-rates of +4.92 V/¿S and -5.04 V/¿S with worst-case settling time of 2.1 ¿S, a voltage gain of 48.97 dB with GBW of 57.27 kHz and phase margin of 78.18 degree were achieved with 10-pF load capacitance and 1.8-V supply voltage. The proposed OTA consumes an overall current of 1.09 ¿A, and occupies a silicon area of 0.008 mm 2 .
DOI:10.1109/SOCDC.2009.5423790