A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors

This paper proposes a new hardening design for an 11 transistors (11T) CMOS memory cell at 32 nm feature size. The proposed hardened memory cell overcomes the problems associated with the previous design by utilizing novel access and refreshing mechanisms. Simulation shows that the data stored in th...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2011-05, Vol.19 (5), p.900-904
Main Authors: Sheng Lin, Yong-Bin Kim, Lombardi, F
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
Circuit simulation
Circuit synthesis
CMOS
CMOS technology
Delay
Design engineering
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Latches
Magnetic and optical mass memories
Memory design
Molecular electronics, nanoelectronics
Nanostructure
Nanotechnology
Predictive models
Radiation hardening
Semiconductor devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
Soft errors
Storage and reproduction of information
Transistors
Very large scale integration
Voltage
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Description
Summary:This paper proposes a new hardening design for an 11 transistors (11T) CMOS memory cell at 32 nm feature size. The proposed hardened memory cell overcomes the problems associated with the previous design by utilizing novel access and refreshing mechanisms. Simulation shows that the data stored in the proposed hardened memory cell does not change even for a transient pulse of more than twice the charge than a conventional memory cell. Moreover it achieves 55% reduction in power delay product compared to the DICE cell (with 12 transistors) providing a significant improvement in soft error tolerance. Simulation results are provided using the predictive technology file for 32 nm feature size in CMOS.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2010.2043271