A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS

A reconfigurable transceiver capable of adapting its signaling mode to the I/O channel is implemented in 45nm CMOS. When configured for single-ended 2/3/4-PAM, it enables 5-to-25Gb/s signaling over on-package interconnect while dissipating 1.6-to-2.6mW/(Gb/s). Over a backplane channel, a differentia...

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Bibliographic Details
Main Authors: Balamurugan, G., O'Mahony, F., Mansuri, M., Jaussi, J.E., Kennedy, J.T., Casper, B.
Format: Conference Proceeding
Language:English
Subjects:
Backplanes
Circuits
Clocks
Degradation
Leg
MOS devices
Packaging
Routing
Transceivers
Voltage
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Description
Summary:A reconfigurable transceiver capable of adapting its signaling mode to the I/O channel is implemented in 45nm CMOS. When configured for single-ended 2/3/4-PAM, it enables 5-to-25Gb/s signaling over on-package interconnect while dissipating 1.6-to-2.6mW/(Gb/s). Over a backplane channel, a differential source series-terminated signaling configuration with TX pre-emphasis and 1-tap DFE allows 10Gb/s signaling with 3.8mW/(Gb/s) power efficiency.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5433826