A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS

This paper presents a fractional-sampling-rate (FSR) CDR that blindly samples the received signal with an ADC at 1.45x the data rate and estimates the data phase using a feedforward architecture for clock and data recovery. The presented architecture reduces the ADC power by 27.3% compared to a 2x C...

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Bibliographic Details
Main Authors: Tyshchenko, O., Sheikholeslami, A., Tamura, H., Tomita, Y., Yamaguchi, H., Kibune, M., Yamamoto, T.
Format: Conference Proceeding
Language:English
Subjects:
Bit error rate
Clocks
Feedforward systems
Filters
Frequency
Jitter
Phase estimation
Sampling methods
Signal analysis
Testing
Online Access:Request full text
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Description
Summary:This paper presents a fractional-sampling-rate (FSR) CDR that blindly samples the received signal with an ADC at 1.45x the data rate and estimates the data phase using a feedforward architecture for clock and data recovery. The presented architecture reduces the ADC power by 27.3% compared to a 2x CDR. Measurements confirm that the FSR CDR recovers data with BER
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5434004