A Self Aligned Contact Process with Improved Surface Planarization

A new self aligned contact technology has been introduced into a 4Mbit DRAM process. The contact hole is overlapping gate and field oxide. A thin nitride/thin poly-Si/oxide multilayer allows a contact hole etch, which does not significantly affect the oxide isolation of the gate and the field oxide....

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Bibliographic Details
Published in:ESSDERC '88: 18th European Solid State Device Research Conference 1988-09, p.c4-503-c4-506
Main Authors: Kusters, K.H., Sesselmann, W., Melzner, H., Friesel, B.
Format: Article
Language:English
Subjects:
Anisotropic magnetoresistance
Capacitors
Dielectrics
Nonhomogeneous media
Oxidation
Planarization
Plasma applications
Random access memory
Surface resistance
Wet etching
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Summary:A new self aligned contact technology has been introduced into a 4Mbit DRAM process. The contact hole is overlapping gate and field oxide. A thin nitride/thin poly-Si/oxide multilayer allows a contact hole etch, which does not significantly affect the oxide isolation of the gate and the field oxide. After acting as etch stop, the poly-Si is changed into oxide by selective oxidation. The new process offers an improved reflow of isolation oxide and contact hole rounding.
DOI:10.1051/jphyscol:19884104