Fault tolerant Block Based Neural Networks

• Main Authors: Haridass, Sai sri Krishna, Hoe, David
• Format: Conference Proceeding
• Language: English
• Subjects: Block based network; Circuit faults; Fabrics; Fault detection; Fault detection and correction; Fault tolerance; Fault tolerant systems; Integrated circuit interconnections; Logic; Network topology; Neural network hardware; Neural networks; Reconfigurable logic
• ISSN: 0094-2898; 2161-8135
• DOI: 10.1109/SSST.2010.5442804

Block Based Neural Networks (BBNNs) have shown to be a practical means for implementing evolvable hardware on reconfigurable fabrics for solving a variety of problems that take advantage of the massive parallelism offered by a neural network approach. This paper proposes a method for obtaining a fault tolerant implementation of BBNNs by using a biologically inspired layered design. At the lowest level, each block has its own online detection and correcting logic combined with sufficient spare components to ensure recovery from permanent and transient errors. Another layer of hierarchy combines the blocks into clusters, where a redundant column of blocks can be used to replace blocks that cannot be repaired at the lowest level. The hierarchical approach is well-suited to a divide-and-conquer approach to genetic programming whereby complex problems are subdivided into smaller parts. The overall approach can be implemented on a reconfigurable fabric.