Design of 8-bit SAR-ADC CMOS

Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18¿m CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic...

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Bibliographic Details
Main Authors: Hassan, Hur A., Halin, Izhal Abdul, Aris, Ishak Bin, Bin Hassan, Mohd Khair
Format: Conference Proceeding
Language:English
Subjects:
Analog-digital conversion
Analog-to-digital converter
CMOS
CMOS technology
comparator
Digital-analog conversion
digital-to-analog converter
Logic arrays
Logic circuits
Low voltage
sample-and-hold
Sampling methods
Switched capacitor circuits
Switches
Switching circuits
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Summary:Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18¿m CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic circuit and digital-to-analog conversion consists of binary weighted capacitor arrays for the differential inputs. The ADC has INL and DNL of 0.45 LSB for supply voltage 1.8V, at sampling rate 200 KS/S and signal to noise ratio distortion is 58.5 dB. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SOC) circuit designs.
DOI:10.1109/SCORED.2009.5443038