System on Programmable Chip Development System

• Main Authors: Lin Fei-yu, Jiao Xi-xiang, Guo Yu-Hui, Zhang Jian-chuan, Qiao Wei-ming, Jing Lan, Wang Yan-Yu, Ma Yun-hai
• Format: Conference Proceeding
• Language: English
• Subjects: Altera; Chip scale packaging; Computer aided instruction; Design automation; Design engineering; Electrical engineering computing; Embedded computing; Embedded system; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; Nios-II; Reduced instruction set computing; system-on-a-programmable-chip (SOPC)
• DOI: 10.1109/ETCS.2010.389

The embedded systems have received increasing research interest in recent years due to its wide usage. This paper presents system on programmable chip (SOPC), a new technology in the embedded systems, to support the development of design projects for undergraduate students in their electrical and computer engineering curriculum. FPGA-based SOPC development board with reduced instruction set computer (RISC) processor cores, a top-down design approach with FPGA computer-aided design tools, a C compiler for the RISC soft-processor core and a large FPGA with on-chip memory are used for a wide variety of student design projects. The course, which includes both software and hardware, can meet the different needs of students from different professional backgrounds and contribute to a better understanding between electrical engineering and computer science and therefore can increase the competitiveness of students.