PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonst...

Full description

Saved in:
Bibliographic Details
Main Authors: Ioannou, D P, Cartier, E, Wang, Y, Mittl, S
Format: Conference Proceeding
Language:English
Subjects:
Electron traps
Gate leakage
HfO 2
High K dielectric materials
High-k dielectrics
High-K gate dielectrics
interface
layer
metal gate
Microelectronics
MOSFETs
PBTI
PBTI recovery
Research and development
Stress
Thickness measurement
Voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V T ) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2010.5488679