PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonst...

Full description

Saved in:
Bibliographic Details
Main Authors: Ioannou, D P, Cartier, E, Wang, Y, Mittl, S
Format: Conference Proceeding
Language:English
Subjects:
Electron traps
Gate leakage
HfO 2
High K dielectric materials
High-k dielectrics
High-K gate dielectrics
interface
layer
metal gate
Microelectronics
MOSFETs
PBTI
PBTI recovery
Research and development
Stress
Thickness measurement
Voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 1048
container_issue
container_start_page 1044
container_title
container_volume
creator Ioannou, D P
Cartier, E
Wang, Y
Mittl, S
description The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V T ) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.
doi_str_mv 10.1109/IRPS.2010.5488679
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_5488679</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5488679</ieee_id><sourcerecordid>5488679</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-c3eb32d2318b90829a60ab55041f59d1b667453e357ef557893785e65256b5053</originalsourceid><addsrcrecordid>eNo9UMtOAjEUrQ8SEfkA46Y_UOxte_tYKkGYCJEorkkH7sQqDmQ6MeHvnUTi2ZycR87iMHYLcgQgw33xunwbKdlJNN5bF87YNRhlDBoV_DnrQ9BegA9w8R9oCZddgAaEk8r2WN8rYY3UoK_YMOdP2cGgssb02WL5uCp4Q_mwrzPxds9T3VJTxU2KO76LR2p4-5E2XzXlzH9ik2Kb9nXX4rNKlDHTls-eF1NeP01W-Yb1qrjLNDzxgL139ngm5i_TYvwwFwkctmKjqdRqqzT4MkivQrQylojSQIVhC6W1zqAmjY4qROeDdh7JokJbokQ9YHd_u4mI1ocmfcfmuD5dpH8BXS9Rfg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs</title><source>IEEE Xplore All Conference Series</source><creator>Ioannou, D P ; Cartier, E ; Wang, Y ; Mittl, S</creator><creatorcontrib>Ioannou, D P ; Cartier, E ; Wang, Y ; Mittl, S</creatorcontrib><description>The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V T ) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.</description><identifier>ISSN: 1541-7026</identifier><identifier>ISBN: 1424454301</identifier><identifier>ISBN: 9781424454303</identifier><identifier>EISSN: 1938-1891</identifier><identifier>EISBN: 1424454298</identifier><identifier>EISBN: 9781424454297</identifier><identifier>EISBN: 9781424454310</identifier><identifier>EISBN: 142445431X</identifier><identifier>DOI: 10.1109/IRPS.2010.5488679</identifier><identifier>LCCN: 82-640313</identifier><language>eng</language><publisher>IEEE</publisher><subject>Electron traps ; Gate leakage ; HfO 2 ; High K dielectric materials ; High-k dielectrics ; High-K gate dielectrics ; interface ; layer ; metal gate ; Microelectronics ; MOSFETs ; PBTI ; PBTI recovery ; Research and development ; Stress ; Thickness measurement ; Voltage</subject><ispartof>2010 IEEE International Reliability Physics Symposium, 2010, p.1044-1048</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5488679$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27923,54553,54918,54930</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5488679$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ioannou, D P</creatorcontrib><creatorcontrib>Cartier, E</creatorcontrib><creatorcontrib>Wang, Y</creatorcontrib><creatorcontrib>Mittl, S</creatorcontrib><title>PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs</title><title>2010 IEEE International Reliability Physics Symposium</title><addtitle>IRPS</addtitle><description>The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V T ) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.</description><subject>Electron traps</subject><subject>Gate leakage</subject><subject>HfO 2</subject><subject>High K dielectric materials</subject><subject>High-k dielectrics</subject><subject>High-K gate dielectrics</subject><subject>interface</subject><subject>layer</subject><subject>metal gate</subject><subject>Microelectronics</subject><subject>MOSFETs</subject><subject>PBTI</subject><subject>PBTI recovery</subject><subject>Research and development</subject><subject>Stress</subject><subject>Thickness measurement</subject><subject>Voltage</subject><issn>1541-7026</issn><issn>1938-1891</issn><isbn>1424454301</isbn><isbn>9781424454303</isbn><isbn>1424454298</isbn><isbn>9781424454297</isbn><isbn>9781424454310</isbn><isbn>142445431X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9UMtOAjEUrQ8SEfkA46Y_UOxte_tYKkGYCJEorkkH7sQqDmQ6MeHvnUTi2ZycR87iMHYLcgQgw33xunwbKdlJNN5bF87YNRhlDBoV_DnrQ9BegA9w8R9oCZddgAaEk8r2WN8rYY3UoK_YMOdP2cGgssb02WL5uCp4Q_mwrzPxds9T3VJTxU2KO76LR2p4-5E2XzXlzH9ik2Kb9nXX4rNKlDHTls-eF1NeP01W-Yb1qrjLNDzxgL139ngm5i_TYvwwFwkctmKjqdRqqzT4MkivQrQylojSQIVhC6W1zqAmjY4qROeDdh7JokJbokQ9YHd_u4mI1ocmfcfmuD5dpH8BXS9Rfg</recordid><startdate>201005</startdate><enddate>201005</enddate><creator>Ioannou, D P</creator><creator>Cartier, E</creator><creator>Wang, Y</creator><creator>Mittl, S</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201005</creationdate><title>PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs</title><author>Ioannou, D P ; Cartier, E ; Wang, Y ; Mittl, S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-c3eb32d2318b90829a60ab55041f59d1b667453e357ef557893785e65256b5053</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Electron traps</topic><topic>Gate leakage</topic><topic>HfO 2</topic><topic>High K dielectric materials</topic><topic>High-k dielectrics</topic><topic>High-K gate dielectrics</topic><topic>interface</topic><topic>layer</topic><topic>metal gate</topic><topic>Microelectronics</topic><topic>MOSFETs</topic><topic>PBTI</topic><topic>PBTI recovery</topic><topic>Research and development</topic><topic>Stress</topic><topic>Thickness measurement</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Ioannou, D P</creatorcontrib><creatorcontrib>Cartier, E</creatorcontrib><creatorcontrib>Wang, Y</creatorcontrib><creatorcontrib>Mittl, S</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ioannou, D P</au><au>Cartier, E</au><au>Wang, Y</au><au>Mittl, S</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs</atitle><btitle>2010 IEEE International Reliability Physics Symposium</btitle><stitle>IRPS</stitle><date>2010-05</date><risdate>2010</risdate><spage>1044</spage><epage>1048</epage><pages>1044-1048</pages><issn>1541-7026</issn><eissn>1938-1891</eissn><isbn>1424454301</isbn><isbn>9781424454303</isbn><eisbn>1424454298</eisbn><eisbn>9781424454297</eisbn><eisbn>9781424454310</eisbn><eisbn>142445431X</eisbn><abstract>The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V T ) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.</abstract><pub>IEEE</pub><doi>10.1109/IRPS.2010.5488679</doi><tpages>5</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1541-7026
ispartof 2010 IEEE International Reliability Physics Symposium, 2010, p.1044-1048
issn 1541-7026
1938-1891
language eng
recordid cdi_ieee_primary_5488679
source IEEE Xplore All Conference Series
subjects Electron traps
Gate leakage
HfO 2
High K dielectric materials
High-k dielectrics
High-K gate dielectrics
interface
layer
metal gate
Microelectronics
MOSFETs
PBTI
PBTI recovery
Research and development
Stress
Thickness measurement
Voltage
title PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T22%3A18%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=PBTI%20response%20to%20interfacial%20layer%20thickness%20variation%20in%20Hf-based%20HKMG%20nFETs&rft.btitle=2010%20IEEE%20International%20Reliability%20Physics%20Symposium&rft.au=Ioannou,%20D%20P&rft.date=2010-05&rft.spage=1044&rft.epage=1048&rft.pages=1044-1048&rft.issn=1541-7026&rft.eissn=1938-1891&rft.isbn=1424454301&rft.isbn_list=9781424454303&rft_id=info:doi/10.1109/IRPS.2010.5488679&rft.eisbn=1424454298&rft.eisbn_list=9781424454297&rft.eisbn_list=9781424454310&rft.eisbn_list=142445431X&rft_dat=%3Cieee_CHZPO%3E5488679%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-c3eb32d2318b90829a60ab55041f59d1b667453e357ef557893785e65256b5053%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5488679&rfr_iscdi=true