Optimal cell design for enhancing reliability characteristics for sub 30 nm NAND Flash memory

One of the critical scaling barriers in sub 30 nm NAND Flash technology node is an abrupt threshold voltage drop of cell transistors by short channel effect. It increases program voltage which leads, in turn, to fatal reliability issues. A simple way to relieve the short channel effect is increasing...

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Bibliographic Details
Main Authors: Eun Suk Cho, Hyun Jung Kim, Byoung Taek Kim, Jai Hyuk Song, Du Heon Song, Jeong-Hyuk Choi, Kang-Deog Suh, Chilhee Chung
Format: Conference Proceeding
Language:English
Subjects:
Boosting
Boron
Business communication
Coupling Rario
Degradation
Doping
Floating Gate
Interference
Mass production
NAND Flash
Nonvolatile memory
Reliability
SCE
Temperature
Threshold voltage
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Summary:One of the critical scaling barriers in sub 30 nm NAND Flash technology node is an abrupt threshold voltage drop of cell transistors by short channel effect. It increases program voltage which leads, in turn, to fatal reliability issues. A simple way to relieve the short channel effect is increasing the channel boron concentration. However it degrades endurance characteristics by deteriorating boosting efficiency on inhibit operation. In this paper, we present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2010.5488763