Verifying thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions

The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we'll indicate the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow hereto which lever...

Full description

Saved in:
Bibliographic Details
Main Authors: Marchal, P, Van der Plas, G, Limaye, P, Mercha, A, Thijs, S, Linten, D, Guruprasad, K, Stucchi, M, Vandevelde, B, Bronckers, S, Minas, N, Cupac, M, Dehan, M, Nelis, M, Agarwal, R, Dehaene, W, Travaly, Y, Beyne, E
Format: Conference Proceeding
Language:English
Subjects:
Costs
Packaging
Power dissipation
Random access memory
Temperature measurement
Temperature sensors
Thermal management
Thermal stresses
Thermomechanical processes
Through-silicon vias
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we'll indicate the importance of extending the chip package co-design flow with thermo-mechanical simulations of the chip stack. We propose a new design flow hereto which leverages information captured by "smart mechanical samples" .
ISSN:1524-766X
2690-8174
DOI:10.1109/VTSA.2010.5488929